Semiconductor Process Engineer

THE ROLE

We are seeking a veteran Semiconductor Process Engineer to serve as our primary technical authority on wet processing and cleaning. As the foundational domain expert on our team, your judgment will set our engineering standards. You will bridge the gap between our core technology and fab-ready equipment, focusing your expertise across three critical pillars:

Materials Science & Fab Compliance

• Conduct comprehensive reviews of mechanical CAD designs and fluid delivery manifolds to ensure 100% compatibility with Ultra-Pure Water (UPW) standards and aggressive fab cleaning chemistries.
• Define the wetted-parts Bill of Materials (BOM), specifying precise fluoropolymer grades (e.g., PFA, PTFE, PEEK) and elastomers to eliminate the risks of metal-ion leaching and particle shedding.
• Proactively identify and resolve SEMI S2/S8 compliance gaps prior to manufacturing.

Test Rig Design & Prototyping

• Collaborate closely with the Engineering team to design Alpha test rigs, including wafer handling mechanisms, chemical delivery manifolds, and cleaning chamber geometries.
• Ensure testing environments accurately simulate real-world fab parameters (flow rates, pressures, and process energetics) to guarantee data validity for tier-one customer stakeholders.
• Validate that physical hardware setups produce stable, reproducible results before test wafers are dispatched for external metrology.

Design of Experiments (DoE) & Data Interpretation

• Architect the DoE matrix and experimental protocols for wafer-level cleaning trials.
• Critically analyze surface analysis outputs (SEM, AFM, particle counts) provided by our external metrology partners.
• Translate metrology data into actionable hardware modifications and process optimizations, driving continuous system improvement.

REQUIREMENTS

Required Qualifications

• 6+ years of hands-on engineering experience in semiconductor wet process, cleaning, or CMP, either within a fab environment or at an equipment manufacturer (OEM).
• Deep technical understanding of defect mechanisms, particle contamination, and fluid dynamics at the wafer surface.
• Expert-level knowledge of semiconductor-grade materials, fluoropolymer plumbing, and UPW system design.
• Ability to read, interpret, and critically evaluate mechanical CAD assemblies (SolidWorks or equivalent).
• Highly self-directed with a proactive, entrepreneurial mindset; capable of defining project scopes, identifying critical risks, and executing autonomously in a lean startup environment.

Preferred Qualifications (Bonus)

• Prior R&D experience with emerging or non-conventional cleaning modalities.
• Familiarity with qualifying new cleaning processes against ITRS/IRDS roadmap requirements.
• An established network within the Taiwan semiconductor ecosystem, including local chemical/material suppliers and the advanced manufacturing supply chain.
• Experience selecting, managing, or collaborating with external metrology partners.

Why join Nable?

• Differentiated Technology: Our approach is meaningfully distinct from megasonic and conventional wet bench methods.

• True Ownership: You are the domain authority. Your decisions on materials, processes, and compliance will directly shape our pilot hardware.

• Strategic Timing: Join at the perfect inflection point—early enough to architect the foundational system, yet backed by proven, de-risked core technology. 

• Equity: Meaningful equity is available for the right candidate who is ready to build and scale alongside us.

How to Apply 

Interested candidates should submit their CV to jamie.pham@nable.ltd